Although power can be optimized across multiple facets from system architecture down to device layout, our offerings are targeted primarily at the RTL level. This representation of the design best models the design specification and intent. The savings achieved with our technology are orthogonal and additive to power savings in other phases of the design.

The two main sources of power in semiconductor devices are active power and leakage power. Our initial focus is on active power which continues to dominate total power even with shrinking process geometries. Process related advancements such as high-K dielectrics and metal gates mitigate the impact of leakage on total power. PwrLite has developed proprietary analysis engines that enable power savings in a holistic fashion across the entire design. Five of these analysis engines constitute unique intellectual property that is currently being filed as patents. Our product portfolio consists of a suite of tools that enable RTL-based power estimation, design analysis and power optimization. Our dynamic power reduction technology is embodied in our flagship product, CooolGate™.

CooolGate is our first product for estimating and significantly reducing dynamic power in semiconductor designs. Our software solutions blend innovation with ease-of-use to directly address a vital customer need for reducing power. We provide two main offerings to our customers:

CooolGate for ASIC: This is an EDA software product that automates the creation of fine-grain clock gating logic for reducing power in semi-conductor ASIC and Custom designs. Use of CooolGate on various customer designs has shown up to 84% reduction in clock power, and as high as 65% reduction in logic switching power. The combination of savings both in clock and logic switching power has yielded on average a reduction of 30% in total power for a variety of designs.

CooolGate for FPGA: There is also a strong need for power savings in FPGAs. PwrLite's power savings technology is directly applicable to the FPGA design market, by virtue of the unique non-intrusive manner of plugging into existing FPGA design flows.

We offer a consulting service as part of an early engagement model. Under this model we apply our patented technology, pilot our tools and work closely with customers to deliver power savings on their semiconductor designs. The company brings its expertise on low power architecture and design into these engagements. The goal is to make the engagement seamless to the project's design flow while delivering up to 40% savings in power for customers.